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The Puma Family 16h is a low-power SoC microarchitecture by AMD. It succeeds Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The ''Beema'' line of processors are aimed at low-power notebooks, and ''Mullins'' are targeting the tablet sector. == Design == The Puma cores use the same microarchitecture as Jaguar, and inherits the design: * Out-of-order execution and Speculative execution, up to 4 CPU cores * Puma does ''not'' feature clustered multi-thread (CMT), meaning that there are no "modules" * Two-way integer execution * Two-way 128-bit wide floating-point and packed integer execution * Integer hardware divider * Puma does ''not'' feature Heterogeneous System Architecture or zero-copy * 32 KiB instruction + 32 KiB data L1 cache per core * 1–2 MiB unified L2 cache shared by two or four cores * Integrated single channel memory controller supporting 64bit DDR3L * 3.1 mm2 area per core * as a SoC (not just an APU) it integrates a Fusion controller hub with the following components: cpu, gpu, memory, and sometimes radios like wifi and cellular. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Puma (microarchitecture)」の詳細全文を読む スポンサード リンク
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